1. Field
A keeper circuit for memory devices is disclosed that compensates for voltage droop in bit lines due to transistor leakage of bit cells.
2. Background
Memory devices are often designed to include a plurality of bit-lines, with each bit-line being coupled to a plurality of bit cells. Selecting a bit cell may comprise turning on an access transistor for the selected bit cell to allow the memory element of the bit cell to pull charge from the bit-line to a circuit ground. Deselecting a bit cell involves turning off the access transistors to prevent the non-selected bit cells from pulling charge from the bit-line. Even after the access transistors for the non-selected bit cells are turned off, these bit-cell transistors still leak some charge and the sum of the entire off device leakage can be equivalent or greater than a single on device current, thus causing a false evaluation. Although the leakage current of a bit cell is small, the leakage becomes a larger issue as memory arrays grow in size. A memory array increases leakage currents proportionately with the number of bit cells coupled to the same bit-line in parallel. When leakage currents approach or exceed the charge pulled by a selected bit cell, the sense circuitry of the memory device may require more time to distinguish, or may be unable to distinguish, a voltage drop due to pulling by a selected bit cell from a voltage drop due to leakage current.
Consequently, a circuit is needed that addresses voltage droop on bit lines for memory devices.